There are various constraints on the design of augmented-reality methods. Not the least of which is that “it’s important to look presentable once you’re strolling round,” Meta analysis scientist Tony Wu advised engineers Tuesday on the IEEE Worldwide Stable State Circuits Convention (ISSCC). “You may’t have a shoebox in your face on a regular basis.”
An AR system additionally have to be light-weight and might’t throw off a number of warmth. And it must be miserly with energy as a result of no one desires to must recharge wearable electronics each couple of hours. Then once more, in the event you’ve bought a flaming-hot shoebox in your face, you may be pleased about a brief battery life.
The 3D chip might monitor two palms concurrently utilizing 40 p.c much less power than a single die might do with just one hand. What’s extra, it did so 40 p.c quicker.
Wu is a part of the Meta group engaged on the silicon smarts to make an AR system, referred to as Aria, that’s as little like a sizzling shoebox as they will make it. A giant a part of the answer, Wu advised engineers, is 3D chip integration expertise. At ISSCC, Meta detailed how the corporate’s prototype AR processor makes use of 3D to do extra in the identical space and with the identical quantity or much less power.
Meta’s prototype chip has each logic and reminiscence on every silicon die. They’re bonded face-to-face, and through-silicon vias carry knowledge and energy to each.Meta
The prototype chip is 2 ICs of equal measurement—4.1 by 3.7 millimeters. They’re bonded collectively in a course of referred to as face-to-face wafer-to-wafer hybrid bonding. Because the title implies, it includes flipping two totally processed wafers so that they’re dealing with one another and bonding them so their interconnects hyperlink collectively immediately. (The “hybrid bonding” half means it’s a direct copper-to-copper connection. No solder wanted.)
The TSMC expertise used for this meant the 2 items of silicon might kind a vertical connection roughly each 2 micrometers. The prototype didn’t totally make use of this density: It required round 33,000 sign connections between the 2 items of silicon and 6 million energy connections. The underside die makes use of through-silicon vias (TSVs)—vertical connections bored down by means of the silicon—to get alerts out of the chip and energy in.
3D stacking meant the group might improve the chip’s computing energy—letting it deal with larger duties—with out including to its measurement. The chip’s machine-learning unit has 4 compute cores on the underside die and 1 megabyte of native reminiscence, however the prime die provides one other 3 MB, accessible by means of 27,000 vertical knowledge channels on the similar pace and power—0.15 picojoules per byte— as in the event that they have been one huge piece of silicon.
The group examined the chip on a machine-learning job important for augmented actuality, hand monitoring. The 3D chip was in a position to monitor two palms concurrently utilizing 40 p.c much less power than a single die might do with just one hand. What’s extra, it did so 40 p.c quicker.
Along with machine studying, the chip can do image-processing duties. 3D made a giant distinction right here, once more. Whereas the 2D model was restricted to compressed photos, the 3D chip can do full HD utilizing the identical quantity of power.
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